The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing more efficient DC-DC converters.
One type of DC-DC converter employs transistor switches that are controlled to periodically transfer charge from an input DC voltage supply to a load device across which the output DC voltage is established. Although there are different ways to realize this type of switching conversion, the most common technique uses inductors and capacitors as energy storage elements and one or more MOSFETs as the switching elements.
To increase the efficiency of the converter, attempts are made to minimize the losses in the switching elements (MOSFETs). There are three types of losses in DC-DC converters: (i) conduction loss, (ii) dynamic loss, and (iii) gate capacitance switching loss. Conduction loss is directly proportional to the on-resistance of the switching transistor which in the case of MOSFETs would be the on-resistance across its source and drain (RDSon). Conduction loss is also directly proportional to the load current and the duty cycle of the control signal driving the switching transistor. Dynamic loss is directly proportional to the rise and fall times of the control signal as well as the magnitude of the input DC voltage and load current. Gate capacitance switching loss is directly proportional to the gate charge Qg, switching frequency and gate voltage. For large load currents, the dynamic and conduction losses are far greater in magnitude than the gate capacitance switching loss. However, the gate capacitance switching loss becomes dominant at lower load currents.
For a given input DC voltage, output voltage, and large load current, in order to reduce the conduction loss, it is desirable to reduce RDSon. This is typically accomplished by employing larger or multiple MOSFETs. Larger MOSFETs, however, have larger gate charge Qg leading to slower control signal rise and fall times and therefore larger dynamic loss. Conversely, in order to reduce the dynamic loss, it is desirable to reduce the gate charge Qg which requires smaller MOSFETs which in result in increased RDSon and therefore increased conduction loss. This trade-off has forced conventional designs to compromise between the two types of losses resulting in a less than optimum design in terms of efficiency. Also, it is desirable to provide a converter which can be controlled to minimize losses for both high and low load currents.